自动布局设计工具(Synopsys IC Compiler)[ISO]

软件简介：

Synopsys IC Compiler可将实体合成、时脉数合成、绕线、良率最佳化，与签证(sign-off)相互关联性整合，避免潜在风险，减少Design ECO的次数。此外，设计限制条件数量大幅成长，複杂度也越来越高，设计人员需花费大量时间来确认限制条件。巨有採用Synopsys IC Compiler后，除缩短人力花费外，更把Synopsys IC Compiler的SDC验证功能变成标準的作业流程，前段设计人员将gate-level的netlist交给后段人员进行佈局及绕线前，做最后确认动作。

　　Synopsys最新的IC Compiler能针对RTL一直到晶片製程，提供时序、区域、耗电量、测试性与良率共同一致的最佳化；可从限制条件中找出相关问题，设计人员利用这些资讯来确认和修正问题，可轻易修正实体设计方面时脉问题，提高工程设计品质及及满足高阶客户需求。

Overview
The Galaxy? Design Platform is an open, integrated design implementation platform with best-in-class tools, enabling advanced IC design. Anchored by Synopsys?industry-leading IC implementation tools and the open Milkyway?database, the Galaxy Design Platform incorporates consistent timing, signal integrity (SI) analysis, common libraries, delay calculation, and constraints from RTL all the way to silicon.

Key Benefits

Includes best-in-class tools
Is built on foundation of PrimeTime? and Milkyway
Ensures convergent flow via consistent timing and common engines
Addresses key challenges including timing, signal integrity, test and power management
Proven for 90 nanometers
Provides fastest path to the best results

Design Challenges
Chip design challenges increase every year. Each advance in silicon process technology brings additional demands just to create a functioning chip. Added to that are higher expectations for performance as well as ever-increasing size. Designers at 130 nanometers and below are finding that they need a complete design toolset that spans the range of today抯 issues and will adapt to tomorrow抯 needs without the overhead of making the individual tools work together.

Timing Closure
Chip timing is affected by many factors. Creating the optimal logic structure and physical implementation is required, as well as factoring in testability and power management, and avoiding signal integrity issues. Designers who attempt to address each concern sequentially find themselves iterating in an attempt to converge on the optimal solution. To get through the process quickly and cleanly, designers need a convergent flow that considers all the constraints up front, picks a good starting point, and refines the design to optimal solution with no surprises during sign-off or after tape-out.

Design for Yield (DFY)
Attaining high yield for nanometer designs is a growing challenge. Reducing yield loss mechanisms has become increasingly dependent on design, not just improvement of the manufacturing process. Although defects are manifested during manufacturing, most can now be prevented during implementation through the use of an effective design-for-yield solution.

Support for CCS Modeling Technology
The Galaxy design platform fully supports the Composite Current Source (CCS) modeling technology. The unified CCS model for timing, noise and power, extends the analysis and optimization capabilities within the Galaxy Design Platform to concurrently address nanometer effects and thereby reduce design margins and minimizing iterations.

Signal Integrity
Many designers have treated signal integrity as a post-processing check, forcing engineers late in the design cycle to face the prospects of missed speed goals, extensive manual modifications or even costly re-spins. What is needed is a platform approach to signal integrity that can prevent the majority of issues and provide sign-off quality checks before the design is committed to silicon.

Power Management
As chips become more complex — especially at 130 nanometers and below — leakage becomes an issue, and power optimization and analysis need to be considered as an integral part of the design implementation flow.

Design for Test
Modern chips spend a significant amount of time on the tester, and the cost of test is an increasing part of chip cost. What is needed is a solution that spans the entire design flow and is capable of meeting chip performance goals, reduces the cost of test, and helps to increase yield.

Design Size
The sheer size of today抯 chips overstresses the capabilities of a design flow built from a collection of point tools. Simply reading and writing ASCII files can consume hours of valuable design time and cause frustrating delays if multiple iterations are needed. At 130 nanometers and below, it is necessary to use a common integrated database to remove the data file bottleneck.

Solution
Using point tools in a mix and match manner is no longer adequate. What is needed is an integrated platform to address the issues created by today抯 designs. Synopsys introduced the Galaxy Design Platform to address today抯 toughest challenges. Galaxy delivers:
Best-in-class tools
A complete solution from RTL to silicon
Integration with the Milkyway database for fast, accurate data transfer
Timing closure
Signal integrity closure with comprehensive prevention, analysis and sign-off
Test closure
Power management
Extensive silicon vendor support, including the latest process nodes
A wide choice of compute platforms

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