Altera (FPGA)电子设计软件

软件类型：行业软件
软件性质：无插件破解软件
操作系统：Windows Vista (32/64 bit) and Windows XP (32/64 bit)
官方网站：http://www.altera.com/products/software/sfw-index.jsp

2009年11月3号，北京—— Altera公司 (NASDAQ: ALTR)今天宣布推出 Quartus® II软件9.1 ——在CPLD、FPGA和HardCopy® ASIC设计方面，业界性能和效能最好的软件。与以前的软件版本相比，Quartus II软件9.1新特性和增强功能将编译时间缩短了20％，编译时间比竞争高密度40-nm和65-nm设计仍然快2到3倍。软件新特性是快速重新编译，对于较小的设计改动，这一特性大大缩短了编译时间，而且还支持Altera最新发布的 Cyclone®IV FPGA 。

Quartus II 软件9.1建立在Altera设计软件一直保持的效能优势基础上。对于高端FPGA，软件实现了业界最快的编译时间，过去5年中，编译时间平均每年缩短 20％。最新版软件编译时间上的优势来自于更高效的布局布线算法，更好的多处理器支持以及更快的时序驱动综合等。

快速重新编译实现了更快的设计迭代

快速重新编译新特性使Quartus II软件能够进一步缩短设计编译时间。运行全编译之后，进行小的工程变更(ECO)设计修改时，快速重新编译特性大大提高了设计人员的效能，与再次运行设计全编译相比，编译时间平均缩短了50％。在时序逼近过程中，快速重新编译保留上次设计改动期间的关键时序，明显提高了设计人员的效率。

扩展了对新Cyclone IV FPGA的器件支持

Quartus II 设计软件9.1支持三种最小的Cyclone IV GX器件，Quartus II设计软件9.1 SP1将支持其他的Cyclone IV器件。如果需要了解今天进行的Cyclone IV系列新闻发布，请访问 http://www.altera.com.cn/corporate/news_room/releases/2009/products/nr-cyclone-iv.html 。这一版本的Quartus II软件还支持 Stratix® IV E EP4SE820 FPGA——业界密度最高的820K逻辑单元(LE) FPGA。为Altera最新FPGA系列提供支持使客户能够马上迅速开始最新的Cyclone和Stratix FPGA设计。

Quartus II软件9.1的其他特性包括：

* 渐进式编译非矩形分区——非矩形区域使用户能够建立更紧凑、更高效的平面布局，更容易实现高质量标准。这一新特性为用户提供了更简单方便的介面，在设计划分过程中进行精确控制。
* 增强SSN分析器工具——这一工具增加了对Arria® II GX FPGA和Stratix IV GX FPGA的支持，在引脚分配期间，及时反馈可能出现的同时开关噪声(SSN)违规问题。
* 新的扩展IP基本包——三个新存储器控制器支持RLDRAM II、QDRII / II+和DDR1/2/3，该基本包增加到14个知识产权(IP)内核。
* 初步支持VHDL 2008——Quartus II软件提供更灵活的语言结构，使用户能够开发可重用的代码结构，继续保持了该软件在语言支持上的领先优势。
* Nios® II处理器——现在提供的“/e”型Nios II软核处理器不再需要许可费用。这一版本还标志着Nios II软件开发工具开始支持Eclipse，提高了软件开发效率。
* 扩展OS支持——现在可以支持Linux SUSE 10。

关于Quartus II软件9.1特性的其他信息，请访问 http://www.altera.com.cn/q2whatsnew 。

Altera软件、嵌入式和DSP市场资深总监Chris Balough评论说：“面临预算更紧张、研发资源减少以及设计周期缩短等挑战，当今的设计团队因此一直在寻找提高效能的好方法。Quartus II软件越来越强的效能优势使我们的客户能够更迅速的将其FPGA推向市场，同时降低了工程开支。”

价格和供货信息

现在可以下载 Quartus II软件9.1订购版和免费的网络版。Quartus II软件订户可以收到ModelSim Altera入门版软件，以及IP基本包的全部许可，它包括14个Altera最流行的IP (DSP和存储器)内核。一个节点锁定的PC许可的年度软件订购价格是2,495美元，可以从 Altera eStore 或者授权分销商那里购买。

Altera简介

Altera®的可编程解决方案帮助系统和半导体公司快速高效地实现创新，突出产品优势，赢得市场竞争。请访问www.altera.com ，或者www.altera.com.cn ，了解Altera FPGA、CPLD和ASIC的详细信息。

What’s new in Quartus II design software version 9.1?

Quartus® II software version 9.1 delivers the #1 performance and productivity for FPGA, CPLD, and HardCopy® ASIC designs. This new release supports Altera’s new lowest cost, lowest power FPGA family—Cyclone® IV GX FPGAs with integrated 3.125-Gbps transceivers. The Cyclone IV GX FPGA family is targeted to high-volume, cost-sensitive applications, enabling you to meet increasing bandwidth requirements while lowering costs. Version 9.1 further extends Quartus II software’s productivity advantage by delivering 20 percent overall compile time reduction over Quartus II software version 9.0, and maintains 2x to 3x faster compile times than the nearest competitor for high-density 65-nm and 40-nm designs. In addition, the new Rapid Recompile feature in version 9.1 reduces compile times by 50 percent (on average) compared to a full compile when small engineering change order (ECO)-type design changes are made. Finally, this release also supports the largest FPGA in the industry—Stratix® IV E EP4SE820 devices.

New Rapid Recompile for Faster Design Iteration

The new Rapid Recompile feature enhances Quartus II software’s ability to further minimize design compilation times. Rapid Recompile maximizes productivity by enabling faster small ECO-type design changes after a full compile, reducing compilation times by 50 percent (on average) versus running another full compile on the design. Rapid Recompile also significantly improves productivity during timing closure by preserving critical timing during late design changes.

Cyclone IV GX FPGA Support

Quartus II software now supports Altera’s new generation of low-cost and low-power FPGAs—Cyclone IV GX FPGAs with integrated transceivers. This transceiver variant in the Cyclone IV FPGA family supports mainstream protocols up to 3.125-Gbps with integrated hard PCIe intellectual property (IP) blocks. Compared to Cyclone III FPGAs with external transceivers, Cyclone IV GX FPGAs consume up to 30 percent less total power. Quartus II software version 9.1 offers PowerPlay Power Analysis and Optimization Technology to achieve the lowest power within your power budget. Start your Cyclone IV GX design with Quartus II software and take advantage of the power and cost savings without sacrificing performance.

The Cyclone IV GX EP4CGX15, EP4CGX22, and EP4CGX30 devices are supported (advanced support) in this release. For more information, please visit the Cyclone IV FPGA page. With this latest addition, Quartus II software offers support for all low-cost, mid-range, and high-performance (11.3-Gbps) transceiver FPGAs.

Industry’s Fastest Compile Times

Quartus II software version 9.1 continues to deliver the industry’s fastest compile times (2X to 3X faster than the nearest competitor for high-density 65-nm and 40-nm designs). Version 9.1 also delivers 20 percent overall compile time reduction over Quartus II software version 9.0 in all design stages. Regardless of which design stage you are at, you will experience faster compile times by upgrading to the latest version 9.1 release. In addition, Quartus II software introduces the new Rapid Recompile feature to extend its leadership in design compilation time.

With version 9.1, you get the following compilation advantages:

* Rapid Recompile for compile-time reduction and timing preservation when making small design changes
* Support for multiprocessors resulting in (on average) 20 percent faster compile times
* Advanced place-and-route algorithms for industry-leading compile times
* Incremental compile support for an additional compile-time reduction of up to 70 percent

Faster Multiprocessor Support with New Parallel Synthesis

Quartus II software is the leader in multi-processor support and is the only FPGA design software that performs parallel processing in all synthesis, place-and-route, static timing analysis, and assembler design stages. Quartus II software also can achieve a 20 percent compilation time saving, on average. In the version 9.1 release, new parallel synthesis support significantly reduces synthesis time for designs with partitions.

Faster Timing-Driven Synthesis

Timing-driven synthesis increases performance of your design by performing synthesis while keeping timing constraints in mind. Version 9.1 delivers an enhanced timing-driven synthesis feature, enabling you to improve design performance in 10 percent less compile time than the previous versions for faster timing closure.

Improved Incremental Compile

Time spent closing timing usually pertains to one or two critical blocks of your design. The incremental compile feature allows you make changes and compile just the critical blocks until timing is closed. This methodology allows you to reduce your compilation times by up to 70 percent compared to a flat compile. Version 9.1 adds more flexibility to close timing and optimize your design with partitions.

Additional Enhancements

* VHDL 2008 Initial Support—Quartus II software maintains its leadership in language support by providing a more flexible and easy-to-use language structure.
* New and Expanded IP Base Suite—Three new and faster memory controllers
* Expanded SSN Analyzer Tool Support—With added support for Stratix IV and Arria® II GX devices, the SSN Analyzer allows you to interactively manage pin assignments and reduce SSN violations, providing faster board design and shorter system-level debug time.
* Non-Rectangular Floorplanning—Non-rectangular regions help create more compact and efficient floorplans, making it easier to achieve quality metrics. Quartus II software version 9.1 helps to create non-rectangular floorplans, which provides more freedom.
* Free Nios II/e Soft Processor—Now includes the lowest-cost Nios II processor core using the fewest FPGA logic and memory resources in the Nios II family.
* Expanded OS Support—Adds SUSE Enterprise 10 support in addition to SUSE Enterprise 9 support.

Device Support

* Stratix IV GX/Stratix IV GT FPGAs—Adds EP4SGX230, EP4SGX180, EP4S40G2, and EP4S100G2 device programming support. New EP4SGX290, EP4S40G5, EP4S100G3, EP4S100G4, EP4S100G5 devices include advanced support.
* Stratix IV E FPGAs—Adds advanced support for the EP4SE820 and the EP4SE230 devices.
* HardCopy III/HardCopy IV ASICs—New HardCopy IV GX compilation support enables design handoff for back-end ASIC processing.
* Arria II GX FPGAs—Adds programming support for EP2AGX65 and EP2AGX45 devices. Removes EP2AGX30 and EP2AGX20 devices from support.
* Removal of Older Families—The ACEXTM 1K, APEXTM 20KC, APEX 20KE, APEX II, FLEX® 6000, FLEX 10K, FLEX 10KA, FLEX 10KE, and HardCopy Stratix device families will be removed from Quartus II software version 9.1 and future releases. The last support for these device families is version 9.0 SP2, which will be available permanently on Altera’s Download Center.

Advanced support includes compilation and pin-out support; programming support includes compilation, pin-out, and device programming (POF) support.

引用
安装指南
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